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JTAG Connections

201.   What is the pin-out of the MAJIC cable?

202.   My RC323xx board has a 26-pin connector, but my MAJIC came with a 24-pin connector. How can I connect them?

203.   Can MAJIC support a JTAG scan chain that includes more devices than just the processor under test?

204.   How do the EJTAG and PCTrace signals on a Broadcom processor map onto the standard EJTAG connector?


 
201. What is the pin-out of the MAJIC cable?
Answer: The pin-out of the cable depends on the debug interface of the processor you are using. EPI provides an application note for each of the supported debug interfaces with complete details on the pin-out and other interface issues. Links to the downloadable PDF versions of those application notes are on the Tech Library page in the Application Notes section.
 
202. My RC323xx board has a 26-pin connector, but my MAJIC came with a 24-pin connector. How can I connect them?
Answer: IDT and EPI agreed upon a standard debug connector; 24-pin with 50mil spacing, documented in the EPI 0380-0181-10 Application Note. However, the IDT 79S134 board and certain other target boards were designed before we settled on this connector, and use a different connector type (26-pin with 100mil spacing).

IDT has built an adapter board that is included with new 79S134 boards.

The following is the connection information for adapting the older style 26-pin (IDT) connector to the standard 24-pin connector.


S134/J23-1  (TRST*)     = EPI-1 (TRST*)
S134/J23-3  (TDI/DINT*) = EPI-3 (TDI/DINT*)
S134/J23-5  (TDO/TPC)   = EPI-5 (TDO/TPC)
S134/J23-7  (TMS)       = EPI-7 (TMS)
S134/J23-9  (TCLK)      = EPI-9 (TCK)
S134/J23-11 (DBugBoot)  = EPI-21 (DebugBoot)
S134/J23-13 (Vcc 3.3)   = EPI-23 (VIO)
S134/J23-15 (PCST0)     = EPI-13 (PCST[0])
S134/J23-17 (PCST1)     = EPI-15 (PCST[1])
S134/J23-19 (PCST2)     = EPI-17 (PCST[2])
S134/J23-21             = n/c
S134/J23-23 (note)      = EPI-11 (RST*)
S134/J23-25 (DCLK)      = EPI-19 (DCLK)

All even-numbered pins are tied to ground.

NOTE: J23-23 is documented as PCST4--reserved. This pin was redefined as a reset signal that is driven by MAJIC to reset the target board.

 
203. Can MAJIC support a JTAG scan chain that includes more devices than just the processor under test?
Answer: Yes, although there are some caveats. When MAJIC initializes the JTAG scan chain, it automatically checks how many devices are attached. If there is one, then it automatically selects that one. If there are more than one, then the user must specify which device on the chain corresponds to the processor under test.

The number of devices is reported in the read-only Ice_Jtag_Tap_Count option. You may view that with EDB's Option Settings editor, or with the DOV command. To specify which TAP controller (the 'state machine' part of the JTAG interface) the MAJIC should connect to for this debug session, you must set the Ice_Jtag_Tap_Select option.

You may set it in your startice.cmd file (after the Ice_Power_Sense option), so you never have to think about it again or, if you want to connect to different devices for different debug sessions, you may set it yourself after you start the debugger, using EDB's Option Settings editor or the EO command.

The devices are numbered from 1 to N, where 1 is the device whose TDO signal is connected to MAJIC, and N is the device whose TDI signal is connected to MAJIC.

Caveats:

1. The Ice_Jtag_Tap_Select option may only be set once--it is not presently changeable during a single debug session. Coming real soon, though, you will be able to launch multiple instances of the debugger to debug multiple processors simultaneously!

2. You may not use standard EJTAG-PCTrace in a multi-device JTAG scan chain, because EJTAG redefines the JTAG signals as PCTrace signals while tracing. Unless your CPU vendor has implemented extensions to address this issue, then you should put the processor on its own JTAG scan chain (perhaps through some jumpers to make chaining optional). Otherwise, you must not enable tracing.

 
204. How do the EJTAG and PCTrace signals on a Broadcom processor map onto the standard EJTAG connector?
Answer: The following table shows the connections for the standard 12-pin EJTAG connector, for full debug support without PCTrace, and the standard 28-pin EJTAG connector for full debug support with PCTrace.
    EJTAG Signal  Pin   |  BCM33xx     BCM7100
    ------------------------------------------
      TRST*        1    |  TRST*       TRSTB_N   
      TDI/DINT     3    |  TDI         TDI       
      TDO/TPC      5    |  TDO         TDO       
      TMS          7    |  TMS         TMS       
      TCK          9    |  TCK         TCK       
      RST*         11   |  (see note below)
    ------------------------------------------
      PCST[0]      13   |  PCST[0]     PCST[0]   
      PCST[1]      15   |  PCST[1]     PCST[1]   
      PCST[2]      17   |  PCST[2]     PCST[2]   
      DCLK         19   |  EBI_CLK     pPCLK
      TPC[2]       21   |  TPC_1       TPC_1     
      PCST2[0]     23   |  PCST[3]     PCST[3]   
      PCST2[1]     25   |  PCST[4]     PCST[4]   
      PCST2[2]     27   |  PCST[5]     PCST[5]   

Note: The RST* pin should be connected to the reset circuit on your board. When RST* is low, the entire board, including the CPU, should be reset.

Please refer to the "MAJIC Interface Guidelines for EJTAG" application note, in the Interface Specifications section of the Tech Library, for full details on the EJTAG connector.

 
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EPI MAJIC® JTAG probes and software products are now available through the Mentor Graphics Corporation. Phone: (408) 487-7364 Fax: (408) 487-7050 email: anita_gibson@mentor.com 1001 Ridder Park Drive, San Jose, CA 95131